The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the electronics industry utilized various methods and structures to produce high speed ECL logic devices. ECL logic devices typically used a differential amplifier with a differential transistor pair that had the two transistors of the differential pair connected to a power supply through collector resistors. Thus, the differential amplifier had a passive pull-up and an active pull-down. As a result, the rising edge of the output signal was slower than the falling edge. The difference between the rise and fall times caused jitter and noise in the output signal of the logic device. In some applications, the jitter resulted in timing differences that slowed the operation of the system using the logic device.
Accordingly, it is desirable to have a method of forming a logic device that provides more closely matched rise and fall times, that reduces jitter, and that facilitates increased system operating frequencies.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain NPN devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention.